请教VHDL的Can't resolve multiple constant drivers 问题

作者：dpirly　栏目：EDA技术

请教VHDL的Can't resolve multiple constant drivers 问题
我写的VHDL数字钟
用QuartusII 5.0 编译的
总是出现 Error: Can't resolve multiple constant drivers for et "reg_minute[5]" at clock.vhd(34) 的错误.
我试着多加了一些访问控制信号还是不管事啊? 请教一下

源代码:
-------------------------------
-- File:clock_core.vhd
--
-------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock_core is
    PORT(
        sys_clk:in std_logic;        --系统时钟
        clk_1hz:in std_logic;        --表时钟

        hour:out std_logic_vector(5 downto 0);    --小时输出
        minute:out std_logic_vector(5 downto 0); --分
        second:out std_logic_vector(5 downto 0); --秒

        inc:in std_logic;    -- 加1
        dec:in std_logic;    -- 减1
        sel:in std_logic_vector(1 downto 0); --选择时\分\秒

        reset:in std_logic;  --复位
        mode:in std_logic    --  走表\设置模式  1->设置  0->走表
        );
end entity;

architecture bhv of clock_core is
    -- 内部寄存器
    signal reg_hour:std_logic_vector(5 downto 0);
    signal reg_minute:std_logic_vector(5 downto 0);
    signal reg_second:std_logic_vector(5 downto 0);
begin
    -- 系统进程
    PROCESS(sys_clk,reset)
    begin
        if sys_clk'event and sys_clk = '1' then

            -- 同步复位
            if mode = '1' and reset = '1' then ---就在这!!!!!!!!
                reg_hour <= "000000";
                reg_minute <= "000000";
                reg_second <= "000000";

            -- 对表
            elsif mode = '1' and reset = '0' then
                case sel is
                    when "00"=>
                        if inc = '1' then
                            reg_hour <= reg_hour + 1;
                        elsif dec = '1' then
                            reg_hour <= reg_hour - 1;
                        end if;
                    when "01"=>
                        if inc = '1' then
                            reg_minute <= reg_minute + 1;
                        elsif dec = '1' then
                            reg_minute <= reg_minute - 1;
                        end if;
                    when "10"=>
                        if inc = '1' then
                            reg_second <= reg_second + 1;
                        elsif dec = '1' then
                            reg_second <= reg_second - 1;
                        end if;
                    when others =>
                        null;
                end case;
            end if;
        end if;
    end PROCESS;

    -- 走表进程
    PROCESS(clk_1hz)
    begin
        if clk_1hz'event and clk_1hz='1' then
            -- 走表模式
            if mode = '0' and reset = '0' then --还有这!!!!!!!!
                reg_second <= reg_second + 1;
                if reg_second = 59  then
                    reg_second <="000

2楼：	>>参与讨论
作者： dpirly 于 2006/12/11 13:45:00 发布：等等啊....

3楼：	>>参与讨论
作者： pearcaoer 于 2006/12/11 14:06:00 发布：电路无法实现 sys_clk'event and sys_clk = '1' clk_1hz'event and clk_1hz='1' 两个地方都有reg_hour=XXXXX,电路无法实现

4楼：

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作者： pearcaoer 于 2006/12/11 14:22:00 发布：

--看这里
CAUSE: In the current design, multiple constant (non-tri-state) drivers are contending for the specified net, which was created by Integrated Synthesis to represent one or more signals. This condition usually occurs when a Verilog Design File (.v) or VHDL Design File (.vhd) contains multiple concurrent assignments to the same signal. Integrated Synthesis attempted to resolve the electrically equivalent assignments, but cannot resolve the contending assignments into a SINGLE equivalent driver.

The message(s) immediately below this message indicate the constant drivers to the net that conflict with the net's first constant driver.

During analysis and elaboration, Integrated Synthesis merges electrically equivalent signals when no pragmas or attributes prevent the merger. As a result, the net NAME specified in this message may not REFER to the signal with multiple concurrent assignments; instead, the message may REFER to a equivalent signal in the same design file that was merged to the problematic signal. For example, in the following code, the signal contention is assigned a VALUE in both the Concurrent Signal Assignment Statement and the PROCESS.html">PROCESS Statement. However, during optimization but prior to conflict checking, Integrated Synthesis may merge contention with its equivalent signal no_contention, and report in this message that no_contention (and not contention) is the net with multiple constant drivers.

contention <= data; --看这里
PROCESS (enable)
BEGIN
   IF enable = '1' THEN
          contention <= '0';    --看这里

       no_contention <= '0';
   ELSE
           contention <= '1';      --看这里

             no_contention <= '1';
   END IF;
END_PROCESS;

ACTION: Check the design for multiple concurrent assignments to the same signal. As explained in the information above, the net NAME specified in this message may REFER to either the signal with multiple concurrent assignments or an equivalent signal that was merged with the problematic signal during optimization.

5楼：	>>参与讨论
作者： dpirly 于 2006/12/11 18:18:00 发布：谢谢我的英文实在是太差了,看的稀里糊涂的

6楼：

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作者： dpirly 于 2006/12/11 18:28:00 发布：

回3楼
" sys_clk'event and sys_clk = '1'
clk_1hz'event and clk_1hz='1'
两个地方都有reg_hour<=XXXXX,电路无法实现"

我的意思是在reg_hour<=XXXXX赋值之前用mode信号区分两个进程的赋值
应该不会出现两个进程同时对一个信号赋值的情况

如果把PROCESS(clk_1hz)中的
            hour <= reg_hour;
            minute <= reg_minute;
            second <= reg_second;
删除就可以编译通过

我又修改了一下，增加了一个新的进程，它检测clk_1hz的下降沿，
把结果输出
PROCESS(clk_1hz,mode)
    begin
        if mode = '0' and reset = '0' then
            if clk_1hz'event and clk_1hz='0' then
                hour <= reg_hour; --在这
                minute <= reg_minute; -- 这
                second <= reg_second; -- 这
            end if;
        end if;
    end PROCESS;
结果还一样，编译失败

* - 本贴最后修改时间：2006-12-11 19:46:18 修改者：dpirly

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作者： pearcaoer 于 2006/12/12 14:54:00 发布：

这个可以编译

-------------------------------
-- File:clock_core.vhd
--
-------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock_core is
    PORT(
        sys_clk:in std_logic;        --系统时钟
        clk_1hz:in std_logic;        --表时钟

        hour:out std_logic_vector(5 downto 0);    --小时输出
        minute:out std_logic_vector(5 downto 0); --分
        second:out std_logic_vector(5 downto 0); --秒

        inc:in std_logic;    -- 加1
        dec:in std_logic;    -- 减1
        sel:in std_logic_vector(1 downto 0); --选择时\分\秒

        reset:in std_logic;  --复位
        mode:in std_logic    --  走表\设置模式  1->设置  0->走表
        );
end entity;

architecture bhv of clock_core is
    -- 内部寄存器
    signal reg_hour:std_logic_vector(5 downto 0);
    signal reg_minute:std_logic_vector(5 downto 0);
    signal reg_second:std_logic_vector(5 downto 0);
    signal tmp_reg_hour:std_logic_vector(5 downto 0);
    signal tmp_reg_minute:std_logic_vector(5 downto 0);
    signal tmp_reg_second:std_logic_vector(5 downto 0);
begin
    -- 系统进程
    PROCESS(sys_clk)
    begin
        if sys_clk'event and sys_clk = '1' then

            -- 同步复位
            if mode = '1' and reset = '1' then ---就在这!!!!!!!!
                tmp_reg_hour <= "000000";
                tmp_reg_minute <= "000000";
                tmp_reg_second <= "000000";

            -- 对表
            elsif mode = '1' and reset = '0' then
                case sel is
                    when "00"=>
                        if inc = '1' then
                            tmp_reg_hour <= tmp_reg_hour + 1;
                        elsif dec = '1' then
                            tmp_reg_hour <= tmp_reg_hour - 1;
                        end if;
                    when "01"=>
                        if inc = '1' then
                            tmp_reg_minute <= tmp_reg_minute + 1;
                        elsif dec = '1' then
                            tmp_reg_minute <= tmp_reg_minute - 1;
                        end if;
                    when "10"=>
                        if inc = '1' then
                            tmp_reg_second <= tmp_reg_second + 1;
                        elsif dec = '1' then
                            tmp_reg_second <= tmp_reg_second - 1;
                        end if;
                    when others =>
                        null;
                end case;
            end if;
        end if;
    end PROCESS;

    -- 走表进程
    PROCESS(clk_1hz,mode)
    begin
        if mode='1' then
            reg_hour <= tmp_reg_hour;
            reg_minute <= tmp_reg_minute;
            reg_second <= tmp_reg_second;

        elsif clk_1hz'event and clk_1hz='1' then
            -- 走表模式
&

8楼：	>>参与讨论
作者： dpirly 于 2006/12/12 18:55:00 发布：谢谢谢谢了不过还是有问题，又仔细看了以下发现里面的问题还挺多呢！ * - 本贴最后修改时间：2006-12-12 21:10:39 修改者：dpirly